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Text File | 1993-06-03 | 3.1 KB | 120 lines | [TEXT/OIUB] |
- `timescale 1 ns / 100 ps
- /* Linear Feedback Shift Register
- * verilog module "HCOUNT"
- * Generated by Macintosh application 'LFSR' 5/17/93 1:30 PM
- * company: Apple Computer
- * project: Display Controller
- * designer: Elmer Fudd
- * prototypes:
- HCOUNT(clk, preset, Q, NewLine);
- HCOUNT(.clk(CLOCK), .preset(PRESET), .Q(Q), .NewLine(TC));
- *
- * The counter reaches terminal count after 640 positive edge clocks.
- * 'NewLine' is asserted high at the end of count.
- * count is preset synchronously by an active low on 'preset'.
- * The counter is free running. It presets itself on every terminal count.
- * The shift register output of the counter is brought out of the module as 'Q'.
- * The counter uses AND (or NAND) gates on the output of the shift register to detect for terminal count of all 'ones'.
- * The main counter consist of 10 registers with 2 taps feedback to the input.
- */
- module HCOUNT (clk, preset, Q, NewLine);
- input clk;
- input preset;
- output NewLine;
- output Q;
- reg [9:0] D;
- reg [9:0] Q;
-
- assign NewLine = &Q;
-
- always @(Q or preset or NewLine)
- begin
- casex ({preset, NewLine}) // synopsys parallel_case full_case
- 'b0?, // preset to value
- 'b?1: // retrigger presets from TC
- begin
- D = 'h139; // preset to seed
- end
- 'b10: // normal counting
- begin
- D[9:1] = Q[8:0];
- D[0] = Q[9] ^ Q[2];
- end
- endcase
- end // always
-
- // Shift register description
- always @(posedge clk)
- begin
- Q = D; // make into D register
- end
- endmodule // HCOUNT
-
- // synopsys translate_off
- module LFSR_Test_Counter(clock, ce, preset, tc);
- input clock;
- input ce;
- input preset;
- output tc;
- reg [31:0] count;
-
- assign tc = ~(count == 0);
-
- always @(posedge clock)
- begin
- if(preset == 0 || count == 0)
- begin
- count = 639;
- end
- else if(ce && count >= 0)
- begin
- count = count - 1;
- end
- end
- endmodule // LFSR_Test_Counter
- /* The Test module compares the LFSR counter with a conventional decrement counter
- * any discrepancy between the two counters will be displayed
- * The number of clocks to terminal count is always displayed
- */
- module Test_HCOUNT;
-
- reg clock;
- reg enable;
- reg ce;
- reg [9:0] Q;
- integer i;
- HCOUNT T0(clock, enable, Q, tc);
- LFSR_Test_Counter T1(clock, ce, enable, tc2);
- initial
- begin
- i = 0;
- clock = 0;
- ce = 1;
- enable = 0;
- #100
- enable = 1;
- #204600
- $finish;
- end
- always
- begin
- #50
- clock = ~clock;
- end
- always @(posedge clock)
- begin
- if(tc == 1)
- begin
- $display("Terminal count occurs at clock #%d", i);
- end
- if(tc != tc2)
- begin
- $display("Discrepancy between LFSR counter and test counter at clock #%d", i);
- $display("LFSR terminal count %b, Test terminal count %b",tc, tc2);
- end
- // $display("%d - ce %b, preset %b ,tc %b, test tc %b, Q %x", i, ce, enable, tc, tc2, Q);
- if(ce) i = i + 1;
- end
- endModule // Test_HCOUNT
- // synopsys translate_on
-